Conventionally, a PLL (Phase-locked loop) circuit is widely used for electric devices including a communication device etc. and it is arranged that an output of the PLL circuit is used as a reference clock signal for a circuit, for example. Due to various factors, the output signal of the PLL circuit includes noises and jitter. Significant noises and jitter components in this clock signal may be a cause of degrading a quality of a digital audio device etc., for example. Therefore, to control the noises and jitter in the output signal of the PLL circuit has been a problem, and a variety of approaches are proposed.
Further, although VCO (Voltage Controlled Oscillator: voltage control oscillating circuit) is used as an oscillator which outputs a signal in a PLL circuit, an arrangement of an A/D convertor+CPU+DDS (Direct Digital Synthesizer) may be used instead of the above-mentioned VCO for the purpose of high-speed control of an oscillation frequency.
FIG. 1 is a block diagram showing the arrangement, in which reference numeral 1 indicates an oscillating circuit, reference numeral 2 shows a buffer circuit, reference numeral denotes a frequency divider for frequency dividing an oscillation output from the above-mentioned oscillating circuit 1, reference numeral 4 indicates a phase comparator for comparing a phase difference between a frequency divided output from the above-mentioned frequency divider 3 and a feedback signal of a PLL loop, and reference numeral 5 shows a loop filter for integrating an output of the above-mentioned phase comparator 4.
Further, reference numeral 6 indicates an A/D converter for converting an output of the above-mentioned loop filter 5 into a digital value, and reference numeral 7 denotes CPU for supplying frequency data to DDS based on the digital data from the above-mentioned A/D converter 6. Reference numeral 8 shows DDS which performs accumulation and addition operation of the frequency data from the above-mentioned CPU based on a clock signal from a reference oscillator 9, carries out D/A conversion therefor, and outputs an analog signal. Reference numeral 10 indicates a frequency divider which frequency divides the analog signal from the above-mentioned DDS 8 and supplies it to the phase comparator 4.
In other words, since the above-mentioned CPU 7 and DDS 8 are included in the PLL loop, the oscillation frequency of DDS 8 is controlled at a high speed so as to reduce the phase difference between the above-mentioned oscillating circuit 1 and a DDS output, thereby constituting a digital phase lock loop which follows the oscillation frequency of the oscillating circuit 1.
As shown in FIG. 1, the arrangement in which DDS is included in the PLL circuit is disclosed in Patent Document 1 below.    Patent Document 1: Japanese Patent Application Publication No. H8-340254
Incidentally, a crystal oscillator is used for the oscillating circuit 1 in the above-mentioned PLL circuit as an oscillation source. This crystal oscillator has a structure in which metal thin films as electrodes are attached to both sides of a strip cut out of a quartz crystal to be in the shape of a thin plate. It acts to vibrate at a constant resonance frequency when an alternate electric field is applied to the electrodes. If a substance adheres onto the electrode of this crystal oscillator, then the resonance frequency decreases in proportion to a mass of the substance, which can be used as a microbalance. This method is referred to as a QCM (Quarts Crystal Microbalance: crystal oscillator microbalance) method.
Then, in technical fields, such as deposition and sputtering, the above-mentioned QCM method is used as a film-thickness meter where the resonance frequency of the crystal oscillator is monitored so that a thickness of a film formed by deposition, sputtering, etc. and a film forming speed are measured. Further, the PLL circuit as shown in FIG. 1 is used as a means for monitoring the resonance frequency of the crystal oscillator.
FIG. 2 shows a block diagram of the film-thickness measuring device, and its basic arrangement is similar to that of the PLL circuit shown in FIG. 1. Therefore, in the film-thickness measuring device shown in FIG. 2, the same reference numeral is used to indicate a block which achieves the same function as that of the arrangement shown in FIG. 1.
In addition, as for the above-mentioned film-thickness measuring device using the QCM method, an oscillating circuit section A is constituted by the oscillating circuit 1 and the buffer circuit 2 as shown in FIG. 2, and the circuit arrangement which is indicated by reference numerals 3 to 10 and phase locked to an output of the buffer circuit 2 constitutes a frequency measurement section B. Further, the crystal oscillator 11 connected to the above-mentioned oscillating circuit 1 is accommodated in a vacuum chamber C where deposition or sputtering is carried out. By means of such an arrangement, the oscillation frequency of the oscillating circuit 1 is measured, and the film thickness and the film forming speed are calculated based on the measured value.
The arrangement in which the crystal oscillator is used as a piezoelectric crystal and the film thickness of the film forming material deposited on the electrode film of the piezoelectric crystal is measured by the QCM method as described above is disclosed in Patent Document 2 below.    Patent Document 2: Japanese Patent Application Publication No. H11-160057